Reading & summarizing: Computer Architecture & Assembly Language

4 weeks left b4 final xam...I'm still lazy...urgh...donno when am i going to transform myself?

Chapter 8: Input & Output

I/O subsytems provides mechanism for comm. between CPU and outside worls.

3 factors must be considered in designing I/O subsystem:

1)Data location: device selection, adress of data within device

2)Data transfer: amount,rate, to or from device

3)Synchronization: output only when device ready; input only when data available

• Location in memory - always identified by a single unsigned integer address
• Data location in I/O world -first specifies a device then depending on type of device, location that maybe as complex as the triple(platter, track, sector) for a disk.
• delay/latency and data rate/bandwidth are independent of the processor clock, determined by the motion of mechanical parts.
• badwidth(specified as peak/burst)- no. of bytes per sec transferred after transmission starts.
  

Standardizing I/O interfaces

• 3 things needed to carry out an I/O data transfer are dependent on the type of I/O involved
• contract between CPU n I/O devices defining the data structure at the device interface
• Programmed I/O: a bit in output register may tell a device to start a specific operation, n a bit in input register may signal the completion of operation of operation to the processor.
  
• long and variable latencies/response times bring a need for I/O interrupts to support synchronization , n high-bandwidth burst of data transmission are synchronized using DMA(direct memory access)

I/O bus structures

• diff. comp systems use diff. degrees of separation between I/O data transmission n memory data transmission.
• Isolated I/O: has 1 set of address, data, n control wires for an I/O bus n another set for a memory bus.
• Shared I/O: shares address and data wires between I/O and memory buses but has diff. control signals for read, write, input and output.
  
• memory-mapped I/O: single bus is used for both I/O and memory. Range of memory addresses is reserved for I/O registers, and these registers are read and written using std load and store instruction. 2 primary motivation: 1)data transfer to and from processor is standardized 2)no. of connections to the processor chip/board is reduced
• early minicomp and microcomp used isolated/shared I/O to increase total address space
• M/M cells are contained in 1/few memory modules
• I/O registers are distributed among diff. I/O device interfaces
• fraction of possible I/O registera addresses will be used in a given system
• may be not all bits of memory word are used in particular device register
• in memory-mapped I/O, unused bits are ignored on a write and return unspecified values on a read.
  

Programmed I/O

• used with devices that p'form operations that take many instruction execution times and do not deliver/demand quantities of data larger than 1 word in hugh-speed burst
• processor has time to execute instructions that read and test control bits frm devices,write control bits to devices, n read n write data.
• primary function of I/O device interface: match speed n protocol of processor bus to what is required by devices.
• control bits going frm processor to device are grouped into 1/more command registers n control signals from device to device passes thru in n out registers respectively.
  
• interface also decodes addresses for just the registers of this device.